1. Field of the Invention
The present invention relates to a muting control circuit, and particularly relates to a muting control circuit in a digital audio data processing circuit.
2. Description of the Prior Art
FIG. 2 shows a receiving circuit of a digital audio interface having a conventional muting control circuit. In FIG. 2, a demodulator 1 is supplied through an input terminal IN with digital audio interface data, e.g., which have been provided from a digital audio disk player (not-shown) and have then been modulated, for example, by a biphase mark modulation system according to EIAJ Standards.
The demodulator 1 demodulates the digital audio interface data by using a clock generated by a PLL (Phase Locked Loop) circuit 2 and generates a data error detection signal upon detection of a data error. The PLL circuit 2 uses the input digital audio interface data as a reference signal so as to control the oscillation frequency of a clock generating VCO (Voltage-Controlled Oscillator) in accordance with the phase difference between the reference signal and the output of the VCO.
The output data of the demodulator 1 are supplied to a digital filter 3 and, at the same time, the clock signal from the demodulator 1 is supplied to a PLL circuit 4. The digital filter 3 performs a filter processing and an oversampling processing on the input data by using a clock signal output from the PLL circuit 4. The PLL circuit 4 uses the output of the demodulator 1 as a reference signal so as to control the oscillation frequency of the clock generating VCO in accordance with the phase difference between the reference signal and the output of the VCO.
The digital audio data oversampled by the digital filter 3 is supplied to a digital-to-analog (hereinafter abbreviated as "D/A") converter 5 so as to be converted into an analog audio signal. The output of the D/A converter 5 is supplied to an output terminal OUT through an analog switch 6.
The output of a muting control circuit 7 is supplied to a control input terminal of the analog switch 6. The muting control circuit 7 is supplied with a data error detection signal from the demodulator 1 and with a phase difference signal from the PLL circuit 2, for example, corresponding to the phase difference between the reference signal and the output of the VCO. In the muting control circuit 7, the phase difference signal is supplied to an unlock detecting circuit 8. The unlock detecting circuit 8 provides an unlock detection signal indicating an unlocked state of the PLL circuit 2 when it detects that the phase difference between the reference signal (i.e., the received data) and and output of the VCO in the PLL circuit 2 exceeds a predetermined value. The unlock detection signal and the data error detection signal from the unlock detecting circuit 8 and the demodulator 1, respectively, are supplied to a trigger input terminal of a timer 10 through an OR gage 9. The timer 10 outputs a muting control signal for a period during which at least one of the unlock detection signal and the data error detection signal exists, and for a predetermined period after both of the unlock detection signal and the data error detection signal have disappeared. The analog switch 6 is off during the presence of the muting control signal, thereby performing muting.
In the above-mentioned arrangement, the data error detection signal disappears after the PLL circuit 2 becomes locked so that a normal demodulation processing is performed in the demodulator 1. Here, in the case where the data error detection signal disappears at the same time as the PLL circuit 2 becomes locked, the duration of the muting control signal, i.e., the muting time T.sub.1 is expressed by, EQU T.sub.1 =t.sub.1 +t.sub.0 ( 1)
where t.sub.1 represents a duration from a point in time when a normal reference signal begins to be supplied to the PLL circuit 2 to a point in time when the PLL circuit 2 becomes locked (this time duration hereinafter being referred to as a "lock time"), and t.sub.0 represents the period of time, determined by the timer 10, for which the muting signal continues after both of the unlock detection signal and the data error detection signal have disappeared. Although the lock time t.sub.1 is a time which can be detected by the unlock detecting circuit 8, it is necessary to establish the period of time t.sub.0 to be equal to or longer than the lock time of the PLL circuit 4 to thereby prevent generation of an abnormal sound or the like. Since the lock time of the PLL circuit 4 depends on the deviation in frequency which the PLL circuit 4 follows, it is necessary to make the period of time t.sub.0 be a sum of the maximum value t.sub.2max of the lock time of the PLL circuit 4 and the margin time t.sub.3 for variations in the lock time of the PLL circuit 4. Accordingly, the equation (1) can be transformed as follows. EQU T.sub.1 =t.sub.1 +t.sub.2max +t.sub.3 ( 2)
In the conventional muting control circuit, therefore, even after the PLL circuits 2 and 4 have become locked, excessive muting is performed for the period of time corresponding to the difference between the maximum value t.sub.2max of the lock time of the PLL circuit 4 and its actual time, and for the margin period of time t.sub.3. Moreover, in the case where a data error detection signal exists even after the PLL circuit 2 has become locked state, the muting time is unnecessarily prolonged because the muting is carried out excessively for the period of t.sub.2max +t.sub.3 after this data error detection signal has disappeared.